Adding HPDL2416 displays to Z80

Introduction

I have enhanced my Z80-based system with dual HPDL2416 intelligent displays. Each HPDL2416 is a sophisticated display module containing four 5×7 dot matrix alphanumeric displays with built-in ASCII decoder, memory, and multiplexing circuitry. This article details the hardware integration, address decoding logic, and programming interface.

Hardware Configuration

System Overview

The display subsystem consists of:

• 2 × HPDL2416 four-character intelligent displays
• Address decoding logic:
  • U8A, U8B (74LS32) – OR gates
  • U3E (74HCT04) – Inverter
  • U9A (74LS139) – 2-to-4 decoder

Memory Mapping

The displays are mapped into the Z80’s I/O space from 08h to 0Fh:

• Display B: 08h-0Bh (when A3=1, A2=0)
• Display A: 0Ch-0Fh (when A3=1, A2=1)

Address Decoding Analysis

Address Decoding Structure

The address decoding uses different address bits for distinct purposes:

1. A7-A4: Must be 0000 for I/O space selection
2. A3, A2: Display selection logic
3. A1, A0: Direct connection to displays for character position

Complete Address Decoding Map

Decoding Logic Analysis

Display Selection (A3, A2)

The combination of A3 and A2 determines which display is active:

Character Position (A1, A0)

A1 and A0 are directly connected to the displays for position selection:

Boolean Equations

Display_Enable = A7·A6·A5·A4·A3    (Active when A7-A4=0000 and A3=1)
Display_B_Select = A3·A2          (Active for 08h-0Bh)
Display_A_Select = A3·A2          (Active for 0Ch-0Fh)

Programming Interface

The HPDL2416 displays are programmed using standard Z80 I/O instructions. Each character position is individually addressable using OUT instructions.

Example: Writing “3K SIST.”

        .ORG $0000       ; Program start

    DI                   ; Disable interrupts

    ; Write to Display B (08h-0Bh)
    LD       A,'.'       ; Rightmost character
    OUT      ($08),A     

    LD       A,'T'       ; Center-Right character
    OUT      ($09),A     

    LD       A,'S'       ; Center-Left character
    OUT      ($0A),A     

    LD       A,'I'       ; Leftmost character
    OUT      ($0B),A     

    ; Write to Display A (0Ch-0Fh)
    LD       A,'S'       ; Rightmost character
    OUT      ($0C),A     

    LD       A,' '       ; Center-Right character
    OUT      ($0D),A     

    LD       A,'K'       ; Center-Left character
    OUT      ($0E),A     

    LD       A,'3'       ; Leftmost character
    OUT      ($0F),A     

Technical Implementation Notes

Hardware Considerations

1. Address Decoding:
   • Clean separation between displays using A3,A2
   • Direct position selection through A1,A0
   • No additional position decoding required
2. Timing:
   • No wait states required
   • Direct memory-mapped interface
   • Characters can be written at full Z80 I/O speed

System Benefits

1. Hardware Simplification:
   • Built-in character generator
   • Integrated refresh circuitry
   • Simple 5V power requirement
2. Software Interface:
   • Direct I/O addressing
   • No complex initialization required
   • Standard Z80 OUT instructions

Conclusion

The HPDL2416 integration provides an elegant solution for alphanumeric display in Z80 systems. The simple address decoding scheme, using A3/A2 for display selection and direct A1/A0 connections for position selection, results in a clean and efficient design. The straightforward programming interface makes it an excellent choice for applications requiring reliable alphanumeric display capabilities.